1. Field of the Invention
The present invention is related to a method of chip burn-in scanning, and particularly to a method that utilizes a data latch of a chip to increase chip burn-in scanning efficiency.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating chip burn-in scanning 100 according to the prior art. As shown in FIG. 1, a pattern generator 101 can write a predetermined logic voltage (a logic-high voltage “1” or a logic-low voltage “0”) to each memory cell of a memory chip 102. The pattern generator 101 can utilize a solid pattern, a checkerboard pattern, a row bar pattern, and/or a column bar pattern to write the predetermined logic voltage to each memory cell of the memory chip 102.
In addition, as shown in FIG. 1, a pass/fail decision unit 104 determines whether a predetermined logic voltage stored in each memory cell of the memory chip 102 is correct, and outputs a determination result corresponding to each memory cell. Then, a test machine 108 reads the determination result corresponding to each memory cell. However, the test machine 108 does not discriminate which memory cell of the memory chip 102 is failed. As long as one memory cell of the memory chip 102 is failed, the test machine 108 determines the memory chip 102 to be failed. Because the chip burn-in scanning 100 spends too much time to determine whether the memory chip 102 is passing or not, the chip burn-in scanning 100 is inefficient for testing the memory chip 102.